Transistors degrade when subjected to voltage stress. In particular, bias temperature instability (BTI) causes threshold voltage degradation over time. Charges are trapped in the transistor gate oxide which causes the threshold voltage to increase in the case of a NMOS transistor. It is known that the aging process may be reversed by applying a voltage of opposite polarity to the gate of the transistor for a short period of time. This voltage releases the charges stored in the gate oxide and causes the threshold voltage to return to approximately its initial value.
The aging problem is especially acute with transistors that are used under the same voltage conditions for extended periods of time. One such use is in the routing circuits of a field programmable gate array (FPGA). The function of the FPGA is specified by the bits of a configuration random access memory (CRAM) that control circuits such as the routing circuits. A single CRAM configuration often is used for the entire life of the device in which the FPGA is connected. This can be many years.
FIG. 1 illustrates a typical routing circuit 100. Circuit 100 comprises eight NMOS pass gate transistors 110, 120, 130, 140, 150, 160, 170, 180. Each transistor includes a source, a drain and a gate. Transistors 110-160 provide inputs A, B, C, D, E, F to circuit 100 and transistors 170, 180 provide outputs. Three configuration bits R are applied to the gates of transistors 110-160 to control whether the transistors are conducting (ON) or not conducting (OFF). A high bit (often represented as a +1) turns the NMOS transistor ON and holds it in that state; and a low bit (often represented as a 0) turns the transistor OFF and holds it in that state. The magnitude of the voltage of a high bit depends on the semiconductor technology in which the transistor is fabricated; and in the most advanced technologies of today may be approximately one volt. The magnitude of the voltage of a low bit is typically zero volts.
Two additional configuration bits R are applied to the gates of transistors 170 and 180 to control whether those transistors are ON or OFF. For example, if the R bits applied to the gates of transistors 140 and 180 are each a 1 and the other bits are zeroes, the output of circuit 100 is D.
Similar circuits of PMOS pass gate transistors will also be familiar to those skilled in the art. In the case of PMOS transistors, a high bit that turns the transistor ON is often represented by a −1 and a low bit by a 0.
It must be emphasized that circuit 100 is only illustrative of many circuits that are configured by control bits that are applied to the gates of pass transistors in the circuit. In many cases, it is expected that the control bits will continue to be applied to the gates for extended periods of time such as many years since the control bits specify the functionality of the circuit in which the FPGA is located.
In anticipation of aging, configuration circuits such as circuit 100 are typically designed with sufficient margins on operating voltages, speed and size that the circuit will perform satisfactorily for many years. These margins, however, impose substantial costs on the circuit in terms of its performance, power requirements and cost of manufacture.